Abstract: This article presents design techniques for an energy-efficient multi-lane receiver (RX) with baud-rate clock and data recovery (CDR), which is essential for high-throughput low-latency ...
Abstract: A 16×16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The ...
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